1. Field of the Invention
The present invention relates to a semiconductor device comprising a memory cell array having a hierarchical bit line structure and a hierarchical word line structure.
2. Description of Related Art
In semiconductor memory devices of recent years such as a DRAM, an increase in capacity and a reduction in size have been achieved, and an increase in the number of memory cells on a bit line causes that a bit-line capacitance tends to increase. Therefore, in order to deal with this performance problem, a hierarchical memory cell array including global bit lines and local bit lines has been employed. In this kind of the hierarchical memory cell array, a plurality of local bit lines are arranged corresponding to each one of global bit lines via a plurality of hierarchical switches, and thereby shortening the length of each local bit line on which a plurality of memory cells are arranged. Further, the hierarchical switches controlling electrical connections between the global bit line and each of the local bit lines enable to read out data stored in a selected memory cell to a local bit line so that the read data can be transmitted to the global bit line through a hierarchical switch. Furthermore, when employing a hierarchical word line structure in addition to a hierarchical bit line structure, a plurality of sub-word lines are arranged corresponding to each one of main word lines via a plurality of sub-word drivers, and thereby shortening the length of each sub-word line. A plurality of memory cells are arranged on each sub-word line. A so-called cross-point cell between a word line and a bit line is defined by a memory cell that is connected to each sub-word line and each local bit line. For example, specific examples of the hierarchical bit line structure or the hierarchical word line structure are disclosed in Patent References 1 and 2.    [Patent Reference 1] Japanese Patent Application Laid-open No. H8-195100 (U.S. Pat. No. 5,612,919)    [Patent Reference 2] Japanese Patent Application Laid-open No. H9-161477 (U.S. Pat. No. 5,831,921)
If the memory cell array becomes large in size, connections of the plurality of hierarchical switches need to be controlled by switch control lines. An increase in the number of the hierarchical switches with an increase in size of the hierarchical memory cell array causes load of the switch control lines to increase, and thereby timing controls to electrically connect between the local bit lines and the global bit line need to be performed differently from one part to another. This is due to that parasitic resistance and capacitance of the switch control lines increase so that time constants thereof increase. There is a skew between access timing of the local and global bit lines and control timing of the hierarchical switches, thereby decreasing access speed. Further, the hierarchical word line structure causes increases in circuit scales of sub-word drivers for driving the sub-word lines and main word drivers for driving the main word lines. In this manner, when employing the hierarchical memory cell array, circuits associated with hierarchization cause an increase in chip size.